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Network equipment and semiconductor manufacturers are in the hot seat with pressure to deliver on outsized capacity demands. They don’t just have to produce ultra-high-density devices powered by cutting-edge application-specific integrated circuit (ASIC) and system-on-a-chip (SoC) solutions. They’ve also got to do it in record time.
The biggest opportunity for speeding silicon production times? Finally eliminating those dated, inefficient testing workflows to fully modernize testing and validation. In other words, standardizing on pre-silicon verification and post-silicon validation testing with an automated, emulation-based approach that is up to the challenge of a virtualized and software-centric and silicon world.
We explored the big picture opportunity for evolving silicon testing in our previous post. Now, let’s dive into the details about how this evolution will work on a technical level.
A brief refresher on the current state
Up until recently, IC and printed circuit board designs were typically verified by emulating silicon with large hardware-based Electronic Design Automation (EDA) emulation systems. Physical test sets would generate traffic into 20 or 30 ports, with different test sets required for each port and interface. It was a slow, expensive process. One that was often breezed through due to market and cost pressures, or skipped entirely given lack of expertise.
In cases where testing went as planned, design issues uncovered after the chip was already manufactured could only be remedied by redesigning and remanufacturing. The result? Thousands of wasted hours, a 30x multiplier on costs and overall delays reaching upwards of a year.
Today’s climate will no longer support waiting until the design is baked into silicon to thoroughly validate chips. Semiconductor manufacturers need to migrate away from hardware solutions for pre-silicon verification and post-silicon validation.
EDA emulation and testing are becoming virtual
The chip industry is virtualizing, replacing hardware solutions with more flexible software. EDA systems are shrinking and becoming virtualized to speed the design process. EDA emulators are following suit.
Pre-silicon testing solutions are also evolving, replacing hardware-based traffic generators with all-software traffic emulators that leverage the traffic emulation capabilities already being used in the network.
Instead of being constrained by a certain number of pre-purchased test ports, virtualized testing can support the scale and automated workflows required to quickly test thousands of ports and easily modify the functional building blocks under test. It provides the agility and power to emulate a variety of protocols and traffic situations.
Libraries of test scenarios enable engineers without the specific expertise to test designs. Instead of taking 50 hours to set up complex network environments, automated workflows can get the job done in just 10 minutes – a 300x acceleration.
Automation is the key to success
The incorporation of software into the pre-silicon stage is still underway but is already enabling extensive chipset design verification before manufacturing:
Continuous pre-silicon testing is reducing chipset development cycles and saving resources.
Increased flexibility and automation are enabling comprehensive testing at scale.
Identifying and resolving defects during design is ensuring chipsets meet the industry’s high-quality standards.
At the end of the day, virtualized pre-silicon chip design verification enables bigger, more complex chips to be designed better, faster and with higher quality.
Spirent is partnering with EDA emulation vendors to integrate automated test emulation into new solutions. Learn more about our Spirent Technology Innovation Program for a deep dive on how an evolved strategy may benefit your silicon testing processes.
